DS90CF363BMT/NOPB feature: No special startup sequence is required between clock/data and/PD pins. Input signal 2 (clock and data) can be applied before or after the device is powered on Support spread spectrum clock frequency modulation up to 100KHz and a deviation of ± 2.5% center spread spectrum or -5% spread spectrum When the input clock is missing and the/PD pin is at the logic high level, the "Input Clock Detection" function will pull all LVDS pairs to the logic low level Supports 18 to 68MHz shift clock • Top notch settings and hold time on TxInput • Tx power consumption<130 mW (typical value) @ 65MHz grayscale • Power consumption 40% lower than BiCMOS similar products • Tx power-saving mode<37 μ W (typical value) • Supports VGA, SVGA, XGA, and dual pixel SXGA Narrow bus reduces cable size and cost • Up to 1.3 Gbps throughput • Up to 170 megabytes per second bandwidth • 345mV (typical) swing LVDS device, achieving low EMI • PLL without external components • Compatible with TIA/EIA-644 LVDS standard • Flat 48 pin TSSOP package • Improved alternative methods: - SN75LVDS84, DS90CF363A
The DS90CF363BMT/NOPB transmitter converts 21 bit CMOS/TTL data into three LVDS (Low Voltage Differential Signal) data streams. The phase-locked transmission clock is transmitted in parallel with the data stream through the fourth LVDS link. Each cycle of the clock is used to sample and transmit 21 bit input data. At a transmission clock frequency of 65 MHz, each LVDS data channel transmits 18 bit RGB data and 3 bit LCD timing and control data (FPLINE) at a rate of 455 Mbps FPFRAME、DRDY）。 When using a 65 MHz clock, the data throughput is 170 MB/second. DS90CF363BMT/NOPB is fixed as a falling edge gating transmitter and can be interoperated with the falling edge gating receiver (DS90CF366) without any conversion logic. This chipset is an ideal means to address EMI and cable size issues related to wide and high-speed TTL interfaces.